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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Features
* IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz with 16KB D- and Icaches * PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications * 4KB on-chip memory (OCM) * Programmable timers * External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices * DMA support for memory and UARTs. - Scatter-gather chaining supported - Four channels * PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI Bus interface * Software accessible event counters * Two serial ports (16750 compatible UART) * One IIC interface * General purpose I/O (GPIO) available * Supports JTAG for board level testing * Internal processor local Bus (PLB) runs at SDRAM interface frequency * Supports PowerPC processor boot from PCI memory - Internal or external PCI Bus Arbiter * Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII) * Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts
Description
Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS SA-27E, 0.18 m (0.11 m Leff) Package: 31mm, 385-ball, enhanced plastic ball grid array (E-PBGA) Power (typical): 1.2W at 200MHz
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While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O Specifications--Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O Specifications--Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Figures
PPC405EP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 31mm, 385-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local IBM sales office.
Product Name PPC405EP PPC405EP PPC405EP PPC405EP PPC405EP PPC405EP Order Part Number1 IBM25PPC405EP-3AA133C IBM25PPC405EP-3AA133CZ IBM25PPC405EP-3AA200C IBM25PPC405EP-3AA200CZ IBM25PPC405EP-3AA266C IBM25PPC405EP-3AA266CZ Processor Frequency 133MHz 133MHz 200MHz 200MHz 266MHz 266MHz Package 31mm, 385 E-PBGA 31mm, 385 E-PBGA 31mm, 385 E-PBGA 31mm, 385 E-PBGA 31mm, 385 E-PBGA 31mm, 385 E-PBGA Rev Level A A A A A A PVR Value 0x51210950 0x51210950 0x51210950 0x51210950 0x51210950 0x51210950 JTAG ID 0x20267049 0x20267049 0x20267049 0x20267049 0x20267049 0x20267049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PowerPC 405EP Embedded Processor User's Manual for details on the register content. Order Part Number Key
IBM25PPC405EP-3AA266Cx
Shipping Package Blank = Tray Z = Tape and reel IBM Part Number Operational Case Temperature Range (-40 C to +85 C) Processor Speed 266 MHz Revision Level
Grade 3 Reliability
Package 31mm, 385 E-PBGA
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PowerPC 405EP Embedded Processor Data Sheet
PPC405EP Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers MMU Power Mgmt DOCM IOCM OCM SRAM
Event Counters
OCM Control
DCRs UART x2
PPC405 Processor Core JTAG 16KB D-Cache DCU Trace ICU
DCR Bus
GPIO
IIC
GPT
16KB I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
MAL
Ethernet x2
Arb
Processor Local Bus (PLB)
SDRAM Controller
External Bus Controller 29-bit addr 16-bit data
PCI Bridge
13-bit addr 32-bit data
66 MHz max (async)
MII
The PPC405EP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Address Map Support
The PPC405EP incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EP processor through the use of mtdcr and mfdcr instructions.
System Memory Address Map 4GB System Memory
Function Subfunction SDRAM, External Peripherals, and PCI Memory Note: Any of the address ranges listed at right may be use for any of the above functions. Peripheral Bus Boot 1 PCI Boot PCI I/O PCI I/O PCI Configuration Registers Interrupt Acknowledge and Special Cycle Local Configuration Registers UART0 UART1 IIC0 Internal Peripherals OPB Arbiter GPIO Controller Registers Ethernet 0 Controller Registers Ethernet 1 Controller Registers
2
Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600800 0xEF600900
End Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6008FF 0xEF6009FF
Size 3712MB 8MB 44MB 6MB 1MB 263MB 2MB 128KB 64KB 56MB 8B 4B 64B 8B 8B 32B 64B 128B 256B 256B
General Use
Boot-up
Notes: 1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved.
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PowerPC 405EP Embedded Processor Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Reserved Clock, Control, and Reset Power Management Interrupt Controller Reserved DMA Controller Registers Reserved Ethernet MAL Registers Event Counters Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB). 0x000 0x010 0x012 0x014 0x018 0x020 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x100 0x140 0x180 0x200 0x204 0x00F 0x011 0x013 0x017 0x01F 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0FF 0x13F 0x17F 0x1FF 0x203 0x3FF 16W 2W 2W 2W 8W 96W 16W 16W 8W 6W 8W 8W 16W 48W 64W 64W 128W 4W 508W
1
Start Address 0x000
End Address 0x3FF
Size 1KW (4KB)1
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: * Low-latency access to critical instructions and data * Performance identical to cache hits without misses * Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor and local memory. This interface is compliant with version 2.2 of the PCI Specification. Features include: * Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter. * PCI bus frequency up to 66MHz - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum * 32-bit PCI address/data bus * Power Management: - PCI Bus Power Management v1.1 compliant * Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI * Buffering between PLB and PCI: - PCI target 64-byte write post buffer - PCI target 96-byte read prefetch buffer - PLB slave 32-byte write post buffer - PLB slave 64-byte read prefetch buffer * Error tracking/status * Supports PCI target side configuration * Supports processor access to all PCI address spaces: - Single-byte PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-byte PCI configuration reads and writes (type 0 and type 1) - PCI interrupt acknowledge
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PowerPC 405EP Embedded Processor Data Sheet
- PCI special cycle * Supports PCI target access to all PLB address spaces * Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to two physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * 11x8 to 13x11 addressing for SDRAM (2 banks) * 32-bit memory interface support * Programmable address compare for each bank of memory * Industry standard 168-pin DIMMS are supported (some configurations) * 266 MHz PPC405EP supports up to 133 MHz memory with PC-133 support * 4MB to 256MB per bank * Programmable address mapping and timing * Auto refresh * Page mode accesses with up to 4 open pages * Power management (self-refresh)
External Peripheral Bus Controller (EBC)
* Supports five banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals * Up to 66MHz operation * Burst and non-burst devices * 8- and 16-bit byte-addressable data bus width support * Latch data on Ready, synchronous or asynchronous * Programmable 2K clock time-out counter with disable for Ready * Programmable access timing per device - 0-255 wait states for non-bursting devices - 0-31 burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address
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PowerPC 405EP Embedded Processor Data Sheet
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS * Programmable address mapping * Peripheral Device pacing with external "Ready"
DMA Controller
* Supports memory-to-memory transfers * Four channels * Scatter/gather capability for programming multiple DMA operations * 32-bit addressing * Address increment or decrement * Internal 32-byte data buffering capability
Serial Interface
* One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided * Internal serial clock to allows a wide range of baud rates * Register compatibility with NS16750 register set * Complete status reporting capability * Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode * Fully programmable serial-interface characteristics * Supports DMA using internal DMA engine
IIC Bus Interface
* Compliant with Phillips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100kHz or 400kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Supports fixed VDD IIC interface * Two independent 4 x 1 byte data buffers
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PowerPC 405EP Embedded Processor Data Sheet
* Twelve memory-mapped, fully programmable configuration registers * One programmable interrupt request signal * Provides full management of all IIC bus protocol * Programmable error recovery
General Purpose IO (GPIO) Controller
* Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses * All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. * Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, threestated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: * Supports seven external and 19 internal interrupts * Edge triggered or level-sensitive * Positive or negative active * Non-critical or critical interrupt to processor core * Programmable critical interrupt priority ordering * Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
* Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation * Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
JTAG
* IEEE 1149.1 test access port * IBM RISCWatch debugger support * JTAG Boundary Scan Description Language (BSDL)
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PowerPC 405EP Embedded Processor Data Sheet
31mm, 385-Ball E-PBGA Package
Top View
Gold Gate Release Corresponds to A1 Ball Location
15.5 TYP
C
Note: All dimensions are in mm.
0.20 C 0.25 C
0.20
A 31.0 27.98 0.35 C
Bottom View
AB Y V T P 31.00.2 M K H F D B B
AC AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 0.65 0.05 SOLDERBALL x 385 0.30 s C A s B s 0.15 s C Thermal Balls
1.27 TYP Mold Compound
PCB Substrate
0.60.1 2.49 REF 2.65 max
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PowerPC 405EP Embedded Processor Data Sheet
Pin Lists
The PPC405EP embedded controller is available in a 31 millimeter, 385-ball E-PBGA package. The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 33 where the signals in the indicated interface group begin.
Signals Listed Alphabetically
Signal Name AGND AVDD BA0 BA1 BankSel0 BankSel1 CAS ClkEn0 ClkEn1 DQM0 DQM1 DQM2 DQM3 EMCMDClk EMCMDIO EMC0Tx0D0 EMC0Tx0D1 EMC0Tx0D2 EMC0Tx0D3 EMC0Tx0En EMC0Tx0Err EMC0Tx1D0 EMC0Tx1D1 EMC0Tx1D2 EMC0Tx1D3 EMC0Tx1En EMC0Tx1Err ExtReset Ball AB21 AC20 Y15 AC16 AB13 AC13 Y14 AB14 AC14 AC10 AA7 W04 U02 Y06 AA5 U03 N03 L01 P03 W01 V03 B15 C14 A15 D14 A16 C15 A03
(Part 1 of 12)
Interface Group Page 37
System
SDRAM SDRAM SDRAM SDRAM
35 35 35 35
SDRAM
35
Ethernet Ethernet
34 34
Ethernet
34
Ethernet Ethernet
34 34
Ethernet
34
Ethernet Ethernet External Slave Peripheral
34 34 35
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball A01 A02 A07 A12 A17 A22 A23 B01 B02 B22 B23 C03 C21 D04 D20 E05 E09 E12 E15 E19 G01 G23 J05 J19 K10-K14 L10-L14 Ground Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls. 38
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball M01 M05 M10-M14 M19 M20 M23 N10-N14 P10-P14 R05 R19 U01 U23 W05 W09 W12 W15 W19 Y04 Y20 AA03 AA21 AB01 AB02 AB22 AB23 AC01 AC02 AC07 AC12 AC17 AC22 AC23 Power Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls. 38
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name GPIO00[PerBLast] GPIO01[TS1E] GPIO02[TS2E] GPIO03[TS1O] GPIO04[TS2O] GPIO05[TS3] GPIO06[TS4] GPIO07[TS5] GPIO08[TS6] GPIO09[TrcClk] GPIO10[PerCS1] GPIO11[PerCS2] GPIO12[PerCS3] GPIO13[PerCS4] GPIO14[PerAddr03] GPIO15[PerAddr04] GPIO16[PerAddr05] GPIO17[IRQ0] GPIO18[IRQ1] GPIO19[IRQ2] GPIO20[IRQ3] GPIO21[IRQ4] GPIO22[IRQ5] GPIO23[IRQ6] GPIO24[UART0_DCD] GPIO25[UART0_DSR] GPIO26[UART0_RI] GPIO27[UART0_DTR] GPIO28[UART1_Rx] GPIO29[UART1_Tx] GPIO30[RejectPkt0] GPIO31[RejectPkt1] Halt IICSCL IICSDA [IRQ0]GPIO17 [IRQ1]GPIO18 [IRQ2]GPIO19 [IRQ3]GPIO20 [IRQ4]GPIO21 [IRQ5]GPIO22 [IRQ6]GPIO23 Ball A09 AA23 Y22 Y23 W21 U20 V23 U21 U22 T21 C02 E03 D03 D05 B04 A04 A05 W22 W23 V21 V22 T22 R20 T23 M04 K01 L04 J01 J02 J03 W20 Y21 C22 AB4 Y01 W22 W23 V21 V22 T22 R20 T23 Interrupts 37 System Internal Peripheral 37 36 System 37
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 Ball AB15 AB16 AB17 AA17 AC18 AA18 AC19 AB19 Y18 AA19 Y19 AA20 AC21 AA14 Y13 SDRAM 35 SDRAM Note: During a CAS cycle MemAddr00 is the least significant bit (lsb) on this bus. 35
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AB12 AA12 AC11 AA11 Y11 AA10 AC9 AB9 AC8 Y09 AA8 AB7 AB6 Y07 AA6 AC5 AB5 AC4 Y05 AA4 AB3 Y03 W03 V04 W02 U04 V02 T04 T02 R04 R03 R02 B11 B09 B19 C17 Power D13 E06 E07 E08 38 SDRAM Note: MemData00 is the most significant bit (msb) on this bus. 35
(Part 6 of 12)
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball E16 E17 E18 E21 F05 F19 F23 G05 G19 H05 H19 H22 K04 K20 K23 M22 N01 P20 P23 T05 T19 T20 U05 U19 V01 V05 V19 W06 W07 W08 W16 W17 W18 Y12 AC06 Power 38
(Part 7 of 12)
Interface Group Page
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 PCIC1/BE1 PCIC2/BE2 PCIC3/BE3 PCIClk PCIDevSel PCIFrame PCIGnt0/Req PCIGnt1 PCIGnt2 PCIIDSel Ball B16 C16 B17 D16 B18 D17 C18 A19 D18 C19 A20 B20 C20 C23 D21 D22 J22 J23 K21 K22 L21 L22 L23 M21 N23 N22 N21 P22 P21 R23 R22 R21 A18 D19 L20 N20 B21 H21 F22 D23 E23 F21 A21 PCI PCI PCI PCI PCI PCI 33 33 33 33 33 33 PCI 33 PCI Note: PCIAD31 is the most significant bit (msb) on this bus. 33
(Part 8 of 12)
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReset PCISErr PCIStop PCITRDY [PerAddr03]GPIO14 [PerAddr04]GPIO15 [PerAddr05]GPIO16 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 [PerBLast]GPIO00 PerClk Ball D15 H20 J21 H23 E20 F20 E22 G20 J20 G22 G21 B04 A04 A05 D07 B06 A06 D08 C07 B07 C08 B08 D09 A08 C09 D10 C10 B10 D11 A10 C11 A11 D12 B12 C12 A13 B13 C13 A14 B14 A09 C04 External Slave Peripheral External Slave Peripheral 35 35 External Slave Peripheral Note: PerAddr3 is the most significant bit (msb) on this bus. 35 PCI PCI PCI PCI 33 33 33 33 PCI 33 PCI PCI PCI PCI
(Part 9 of 12)
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerCS0 [PerCS1]GPIO10 [PerCS2]GPIO11 [PerCS3]GPIO12 [PerCS4]GPIO13 PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerOE PerReady PerR/W PerWBE0 PerWBE1 [PerWE]PCIINT PHY0Col0 PHY0Col1 PHY0CrS0 PHY0CrS1 PHY0Rx0Clk PHY0Rx0D0 PHY0Rx0D1 PHY0Rx0D2 PHY0Rx0D3 PHY0Rx0DV PHY0Rx0Err PHY0Rx1Clk PHY0Rx1D0 PHY0Rx1D1 PHY0Rx1D2 PHY0Rx1D3 Ball E04 C02 E03 D03 D05 P02 N04 P01 M02 M03 L02 L03 K02 K03 H01 J04 G02 G04 H04 F01 D01 F04 B03 D02 F03 E01 D15 AB8 C05 AA9 B05 AB10 Y16 AA22 AA16 AA13 Y10 AB11 E02 R01 H03 G03 F02 Ethernet 34 Ethernet Ethernet Ethernet 34 34 34 Ethernet 34 External Slave Peripheral Ethernet Ethernet Ethernet 35 34 34 34 External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral 35 35 35 35 External Slave Peripheral Note: PerData00 is the most significant bit (msb) on this bus. 35 External Slave Peripheral 35
(Part 10 of 12)
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PHY0Rx1DV PHY0Rx1Err PHY0Tx0Clk PHY0Tx1Clk SysClk RAS [RejectPkt0]GPIO30 [RejectPkt1]GPIO31 Reserved SysErr SysReset TCK TDI TDO TestEn TMS TRST [TS1E]GPIO01 [TS2E]GPIO02 [TS1O]GPIO03 [TS2O]GPIO04 [TS3]GPIO05 [TS4]GPIO06 [TS5]GPIO07 [TS6]GPIO08 [TrcClk]GPIO09 UART0_CTS [UART0_DCD]GPIO24 [UART0_DSR]GPIO25 [UART0_DTR]GPIO27 [UART0_RI]GPIO26 UART0_RTS UART0_Rx UART0_Tx [UART1_Rx]GPIO28 [UART1_Tx]GPIO29 Ball D06 C01 Y08 C06 AB18 AA15 W20 Y21 - Y17 AB20 Y02 AA1 AA2 V20 AC3 H02 AA23 Y22 Y23 W21 U20 V23 U21 U22 T21 T03 M04 K01 J01 L04 N02 T01 P04 J02 J03 Internal Peripheral 36 Internal Peripheral 36 Trace 38 Trace 38 Ethernet Ethernet Ethernet System SDRAM System System Other System System JTAG JTAG JTAG System JTAG JTAG
(Part 11 of 12)
Interface Group Page 34 34 34 37 35 37 37 38 37 37 37 37 37 37 37 37
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE Ball E10 E11 E13 E14 K05 K19 L05 L19 Power N05 N19 P05 P19 W10 W11 W13 W14 AC15 SDRAM 35 38
(Part 12 of 12)
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Signal Name GND GND ExtReset GPIO15[PerAddr04] GPIO16[PerAddr05] PerAddr08 GND PerAddr15 GPIO00[PerBLast] PerAddr21 PerAddr23 GND PerAddr27 PerAddr30 EMC0Tx1D2 EMC0Tx1En GND PCIC0/BE0 PCIAD07 PCIAD10 PCIIDSel GND GND Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 GND GND PerReady GPIO14[PerAddr03] PHY0CrS1 PerAddr07 PerAddr11 PerAddr13 OVDD PerAddr19 OVDD PerAddr25 PerAddr28 PerAddr31 EMC0Tx1D0 PCIAD00 PCIAD02 PCIAD04 OVDD PCIAD11 PCIClk GND GND
(Part 1 of 6)
Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 Signal Name PHY0Rx1Err GPIO10[PerCS1] GND PerClk PHY0Col1 PHY0Tx1Clk PerAddr10 PerAddr12 PerAddr16 PerAddr18 PerAddr22 PerAddr26 PerAddr29 EMC0Tx1D1 EMC0Tx1Err PCIAD01 OVDD PCIAD06 PCIAD09 PCIAD12 GND Halt PCIAD13 Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Signal Name PerData15 PerR/W GPIO12[PerCS3] GND GPIO13[PerCS4] PHY0Rx1DV PerAddr06 PerAddr09 PerAddr14 PerAddr17 PerAddr20 PerAddr24 OVDD EMC0Tx1D3 PCIINT[PerWE] PCIAD03 PCIAD05 PCIAD08 PCIC1/BE1 GND PCIAD14 PCIAD15 PCIGnt0/Req
Signal Name
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 Signal Name PerWBE1 PHY0Rx1Clk GPIO11[PerCS2] PerCS0 GND OVDD OVDD OVDD GND VDD VDD GND VDD VDD GND OVDD OVDD OVDD GND PCIReq0/Gnt OVDD PCIReq2 PCIGnt1 Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 PerData14 PHY0Rx1D3 PerWBE0 PerOE OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PCIReq1 PCIGnt2 PCIFrame OVDD
(Part 2 of 6)
Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 Signal Name GND PerData11 PHY0Rx1D2 PerData12 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PCIReset PCITRDY PCIStop GND Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 Signal Name PerData09 TRST PHY0Rx1D1 PerData13 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PCIIRDY PCIDevSel OVDD PCIPErr
Signal Name
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 Signal Name GPIO27[UART0_DTR] GPIO28[UART1_Rx] GPIO29[UART1_Tx] PerData10 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND PCISErr PCIParity PCIAD16 PCIAD17 Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23
(Part 3 of 6)
Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 Signal Name EMC0Tx0D2 PerData05 PerData06 GPIO26[UART0_RI] VDD No ball No ball No ball No ball GND GND GND GND GND No ball No ball No ball No ball VDD PCIC2/BE2 PCIAD20 PCIAD21 PCIAD22 Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 GND PerData03 PerData04 GPIO24[UART0_DCD] GND No ball No ball No ball No ball GND GND GND GND GND No ball No ball No ball No ball GND GND PCIAD23 OVDD GND Signal Name
Signal Name GPIO25[UART0_DSR] PerData07 PerData08 OVDD VDD No ball No ball No ball No ball GND GND GND GND GND No ball No ball No ball No ball VDD OVDD PCIAD18 PCIAD19 OVDD
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 Signal Name OVDD UART0_RTS EMC0Tx0D1 PerData01 VDD No ball No ball No ball No ball GND GND GND GND GND No ball No ball No ball No ball VDD PCIC3/BE3 PCIAD26 PCIAD25 PCIAD24 Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 PerData02 PerData00 EMC0Tx0D3 UART0_Tx VDD No ball No ball No ball No ball GND GND GND GND GND No ball No ball No ball No ball VDD OVDD PCIAD28 PCIAD27 OVDD
(Part 4 of 6)
Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 Signal Name PHY0Rx1D0 MemData31 MemData30 MemData29 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND GPIO22[IRQ5] PCIAD31 PCIAD30 PCIAD29 Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 Signal Name UART0_Rx MemData28 UART0_CTS MemData27 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD OVDD GPIO09[TrcClk] GPIO21[IRQ4] GPIO23[IRQ6]
Signal Name
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 Signal Name GND DQM3 EMC0Tx0D0 MemData25 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD GPIO05[TS3] GPIO07[TS5] GPIO08[TS6] GND Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 OVDD MemData26 EMC0Tx0Err MemData23 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD TestEn GPIO19[IRQ2] GPIO20[IRQ3] GPIO06[TS4]
(Part 5 of 6)
Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 Signal Name EMC0Tx0En MemData24 MemData22 DQM2 GND OVDD OVDD OVDD GND VDD VDD GND VDD VDD GND OVDD OVDD OVDD GND GPIO30[RejectPkt0] GPIO04[TS2O] GPIO17[IRQ0] GPIO18[IRQ1] Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Signal Name IICSDA TCK MemData21 GND MemData18 EMC0MDClk MemData13 PHY0Tx0Clk MemData09 PHY0Rx0DV MemData04 OVDD MemClkOut1 CAS BA0 PHY0Rx0D0 SysErr MemAddr08 MemAddr10 GND GPIO31[RejectPkt1] GPIO02[TS2E] GPIO03[TS1O]
Signal Name
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PowerPC 405EP Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 TDI TDO GND MemData19 EMC0MDIO MemData14 DQM1 MemData10 PHY0CrS0 MemData05 MemData03 MemData01 PHY0Rx0D3 MemClkOut0 RAS PHY0Rx0D2 MemAddr03 MemAddr05 MemAddr09 MemAddr11 GND PHY0Rx0D1 GPIO01[TS1E] Signal Name Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 GND GND MemData20 IICSCL MemData16 MemData12 MemData11 PHY0Col0 MemData07 PHY0Rx0Clk PHY0Rx0Err MemData00 BankSel0 ClkEn0 MemAddr00 MemAddr01 MemAddr02 SysClk MemAddr07 SysReset AGND GND GND
(Part 6 of 6)
Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Signal Name GND GND TMS MemData17 MemData15 OVDD GND MemData08 MemData06 DQM0 MemData02 GND BankSel1 ClkEn1 WE BA1 GND MemAddr04 MemAddr06 AVDD MemAddr12 GND GND Ball Signal Name
Signal Name
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PowerPC 405EP Embedded Processor Data Sheet
Signal List
The following table provides a summary of the number of package pins associated with each functional interface group.
Pin Summary
Group
Nonmultiplexed Multiplexed Total Signal Pins OVDD VDD Gnd Thermal (and Gnd) Reserved Total Pins
No. of Pins
215 33 248 43 16 53 25 0 385
In the table "Signal Functional Description" on page 33, each external signal is listed along with a short description of the signal function. Active-low signals (for example, RAS) are marked with an overline. Please see "Signals Listed Alphabetically" on page 13 for the pin (ball) number to which each signal is assigned. Multiplexed Pins Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in "Signals Listed Alphabetically" on page 13. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, in the PCI interface PCIC3:0/BE3:0 serves as both Command and Byte Enable signals. In this example, the pins are also bidirectional, serving as both inputs and outputs. Intialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Initialization" on page 50). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V (10k to +5V can be used on 5V tolerant I/Os) and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor.
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405EP. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pull-up and pull-down terminations as specified in the "Signal Functional Description" on page 33, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows: * Peripheral interface--PerAddr03:31, PerData00:15, and all of the control signals are driven by default. Terminate PerReadyhigh. * SDRAM--Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405EP to actively drive all of the SDRAM address, data, and control signals. * PCI--The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following: - Strap the PPC405EP to disable the internal PCI arbiter. - Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3k resistors to +3.3V. - Terminate PCIReq1:2 to +3.3V. - Terminate PCIReq0/Gnt to GND. For selected interfaces, it is possible to turn off input receivers for some or all of the signals on that interface. Control for this receiver gating is in register CPC0_CR1. When this gating capability is applied to unused signals, it is not necessary to strap them. Refer to the PowerPC 405EP Embedded Processor User's Manual for details. External Bus Control Signals All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405EP Embedded Processor User's Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405EP. Please refer to "Signals Listed Alphabetically" on page 13 for the pin number to which each signal is assigned.
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Signal Functional Description
(Part 1 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 32.
Signal Name Description I/O Type
Notes
PCI Interface
PCIAD31:00 PCIC3:0/BE3:0 PCIClk PCIFrame PCI Address/Data Bus. Multiplexed address and data bus. PCI bus command and byte enables. PCIClk is used as the asynchronous PCI clock when in asynch mode. PCIFrame is driven by the current PCI bus master to indicate the beginning and duration of a PCI access. PCI parity. Parity is even across PCIAD00:31 and PCIC3:0/BE3:0. PCIParity is valid one cycle after either an address or data phase. The PCI device that drove PCIAD00:31 is responsible for driving PCIParity on the next PCI bus clock. PCIIRDY is driven by the current PCI bus master. Assertion of PCIIRDY indicates that the PCI initiator is ready to transfer data. The target of the current PCI transaction drives PCITRDY. Assertion of PCITRDY indicates that the PCI target is ready to transfer data. The target of the current PCI transaction can assert PCIStop to indicate to the requesting PCI master that it wants to end the current transaction. PCIDevSel is driven by the target of the current PCI transaction. A PCI target asserts PCIDevSel when it has decoded an address and command encoding and claims the transaction. PCIIDSel is used during configuration cycles to select the PCI slave interface for configuration. PCI interrupt. Open-drain output (two states; 0 or open circuit) or Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. PCISErr is used for reporting address parity errors or catastrophic failures detected by a PCI target. PCIPErr is used for reporting data parity errors on PCI transactions. PCIPErr is driven active by the device receiving PCIAD00:31, PCIC3:0/BE3:0, and PCIParity, two PCI clocks following the data in which bad parity is detected. PCI specific reset. Multipurpose signal, used as PCIReq0 when internal arbiter is used, and as Gnt when external arbiter is used. I/O I/O I I/O 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 2
PCIParity
I/O
PCIIRDY
I/O
2
PCITRDY
I/O
2
PCIStop
I/O
2
PCIDevSel
I/O
2
PCIIDSel
I
PCIINT
O
PCISErr
I/O
2
PCIPErr
I/O
2
PCIReset PCIReq0/Gnt
O I
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PowerPC 405EP Embedded Processor Data Sheet
Signal Functional Description
(Part 2 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 32.
Signal Name PCIReq1:2 Description PCIReq input when internal arbiter is used. Gnt0 when internal arbiter is used or Req when external arbiter is used. PCIGnt output when internal arbiter is used. I/O I Type 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
Notes
PCIGnt0/Req
O
PCIGnt1:2
O
Ethernet Interface
PHY0Rx0:1D3:0 EMC0Tx0:1D3:0 PHY0Rx0:1Err PHY0Rx0:1Clk Received data. This is a nibble wide bus from the PHY. The data is synchronous with the PHY0RxClk. Transmit data. A nibble wide data bus towards the net. The data is synchronous to the PHY0TxClk. Receive Error. This signal comes from the PHY and is synchronous to the PHY0RxClk. Receive Medium clock. This signal is generated by the PHY. Receive Data Valid. Data on the Data Bus is valid when this signal is activated. Deassertion of this signal indicates end of the frame reception. Carrier Sense signal from the PHY. This is an asynchronous signal. Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHYTxClk. It informs the PHY that an error was detected. Transmit Enable. This signal is driven by the EMAC to the PHY. Data is valid during the active state of this signal. Deassertion of this signal indicates end of frame transmission. This signal is synchronous to the PHY0TxClk. This clock comes from the PHY and is the Medium Transmit clock. Collision signal from the PHY. This is an asynchronous signal. Management Data Clock. The MDClk is sourced to the PHY. Management information is transferred synchronously with respect to this clock. Management Data Input/Output is a bidirectional signal between the Ethernet controller and the PHY. It is used to transfer control and status information. I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1 6 1 1
PHY0Rx0:1DV
I
1
PHY0CrS0:1
I
1
EMC0Tx0:1Err
O
6
EMC0Tx0:1En
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
PHY0Tx0:1Clk PHY0Col0:1
I I
1 1
EMC0MDClk
O
EMC0MDIO
I/O
1
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PowerPC 405EP Embedded Processor Data Sheet
Signal Functional Description
(Part 3 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 32.
Signal Name Description I/O Type
Notes
SDRAM Interface
Memory data bus. Notes: 1. MemData00 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr00 is the least significant bit (lsb). Bank Address supporting up to 4 internal banks. Row Address Strobe. Column Address Strobe. DQM for byte lane: 0 (MemData00:7), 1 (MemData08:15), 2 (MemData16:23), and 3 (MemData24:31) Select up to two external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer.
MemData00:31
I/O
3.3V LVTTL
MemAddr12:00
O
3.3V LVTTL
BA1:0 RAS CAS
O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
O
3.3V LVTTL
BankSel0:1 WE ClkEn0:1 MemClkOut0:1
O O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Slave Peripheral Interface
PerData00:15 PerAddr03:05 PerAddr06:31 Peripheral data bus. Note: PerData00 is the most significant bit (msb) on this bus. Peripheral address bus. Note: PerAddr03 is the most significant bit (msb) on this bus. As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either the pripheral controller or the DMA controller depending upon the type of transfer involved. Peripheral write enable. Low when any of the two PerWBE0:1 write byte enables are low. To access this function, software must toggle a DCR bit. Peripheral chip select bank 0. Four additional peripheral chip selects To access this function, software must toggle a DCR bit. I/O I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1 1
PerWBE0:1
I/O
5V tolerant 3.3V LVTTL
1, 7
[PerWE]
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 7 1, 7
PerCS0 [PerCS1:4]
O O
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Signal Functional Description
(Part 4 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 32.
Signal Name PerOE Description Used by either peripheral controller or DMA controller depending upon the type of transfer involved. Used by the PPC405EP as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Ready to transfer data. Used to indicates the last transfer of a memory access. To access this function, software must toggle a DCR bit. Peripheral clock to be used by peripheral slaves. Peripheral reset to be used by peripheral slaves. I/O O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
7
PerR/W
I/O
1
PerReady [PerBLast] PerClk ExtReset
I I/O O O
1 1, 7
Internal Peripheral Interface
UART0_Rx UART0_Tx [UART0_DCD] [UART0_DSR] UART0_CTS [UART0_DTR] UART0_RTS [UART0_RI] [UART1_Rx] [UART1_Tx] IICSCL IICSDA UART0 Serial Data In. UART0 Serial Data Out. UART0 Data Carrier Detect. To access this function, software must toggle a DCR bit. UART0 Data Set Ready. To access this function, software must toggle a DCR bit. UART0 Clear To Send. UART0 Data Terminal Ready. To access this function, software must toggle a DCR bit. UART0 Request To Send. UART0 Ring Indicator. To access this function, software must toggle a DCR bit. UART1 Serial Data In. To access this function, software must toggle a DCR bit. UART1 Serial Data Out. To access this function, software must toggle a DCR bit. IIC Serial Clock. IIC Serial Data. I O I I I O O I I O I/O I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 3.3V IIC 3.3V IIC 1 6 1 1 1 6 6 1 1 6 1, 2 1, 2
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Signal Functional Description
(Part 5 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 32.
Signal Name Description I/O Type
Notes
Interrupts Interface
[IRQ0:6] Interrupt requests To access this function, software must toggle a DCR bit. I 5V tolerant 3.3V LVTTL 1
JTAG Interface
TDI TMS TDO TCK TRST Test data in. JTAG test mode select. Test data out. JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405EP. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4
System Interface
SysReset Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an opendrain output (two states; 0 or open circuit). Set to 1 when a Machine Check is generated. Halt from external debugger. General Purpose I/O. All of the GPIO signals are multiplexed with other signals. Test Enable. Used only for manufacturing tests. Pull down for normal operation. Main system clock input. External request to reject a packet. Clean voltage input for the PLL. Clean Ground input for the PLL. I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1.8V CMOS w/pull-down 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 2 1, 6 1, 2
SysErr Halt GPIO00:31 TestEn SysClk [RejectPkt0:1] AVDD AGND
O I I/O I I I I I
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Signal Functional Description
(Part 6 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 32.
Signal Name Description I/O Type
Notes
Trace Interface
[TS1E] [TS2E] [TS1O] [TS2O] [TS3:6] Even Trace execution status. To access this function, software must toggle a DCR bit Odd Trace execution status. To access this function, software must toggle a DCR bit Trace status. To access this function, software must toggle a DCR bit Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit Note: Initialization strapping must hold this pin low (0) during reset. O O O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 6 1, 6 1, 6
[TrcClk]
O
5V tolerant 3.3V LVTTL
1, 6
Power
GND OVDD VDD Ground Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls. Output driver voltage--3.3V. Logic voltage--1.8V. na na na na na na na na na
Other pins
Reserved Reserved pins. Do not make voltage, ground, or signal connections to these pins. na na na
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Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage Input Voltage (1.8V CMOS receivers) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Note: All specified voltages are with respect to GND. Symbol VDD OVDD AVDD VIN VIN VIN TSTG TC Value 0 to +1.95 0 to +3.6 0 to +1.95 0 to +1.95 0 to +3.6 0 to +5.5 -55 to +150 -40 to +120 Unit V V V V V V
C C
Package Thermal Specifications
The PPC405EP is designed to operate within a case temperature range of -40C to +85C. Thermal resistance values for the E-PBGA packages in a convection environment are as follows:
Package--Thermal Resistance 31mm, 385-balls--Junction-to-Case 31mm, 385-balls--Case-to-Ambient1 Note: 1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax - PxJC, where TJ Max is maximum junction temperature and P is power consumption. Symbol 0 (0) Airflow ft/min (m/sec) 100 (0.51) 2 16.8 200 (1.02) 2 16.1 C/W C/W Unit
JC CA
2 17.8
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PowerPC 405EP Embedded Processor Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications.
Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (1.8V CMOS receivers) Input Logic High (3.3V PCI receivers) Input Logic High (3.3V LVTTL, 5V tolerant receivers) Input Logic Low (1.8V CMOS receivers) Input Logic Low (3.3V PCI receivers) Input Logic Low (3.3V LVTTL, 5V tolerant receivers) Output Logic High (3.3V PCI receivers) Output Logic High (3.3V LVTTL, 5V tolerant receivers) Output Logic Low (3.3V PCI receivers) Output Logic Low (3.3V LVTTL, 5V tolerant receivers) Input Leakage Current (no pull-up or pulldown) Input Leakage Current (with internal pulldown) 5V Tolerant I/O Input Current 1 Input Max Allowable Overshoot (1.8V CMOS receivers) Input Max Allowable Overshoot (3.3V LVTTL, 5V tolerant receivers) Input Max Allowable Undershoot (3.3V LVTTL, 5V tolerant receivers) Output Max Allowable Overshoot (3.3V LVTTL, 5V tolerant receivers) Output Max Allowable Undershoot (3.3V LVTTL, 5V tolerant receivers) Case Temperature Note: 1. See "5V-Tolerant Input Current" on page 41 Symbol VDD OVDD AVDD VIH VIH VIH VIL VIL VIL VOH VOH VOL VOL IIL1 IIL2 IIL4 VIMAO1.8 VIMAO VIMAU VOMAO VOMAU TC -0.6 -40 +85 -0.6 +5.5 Minimum +1.65 +3.0 +1.65 0.65VDD 0.5OVDD +2.0 0 -0.5 0 0.9OVDD +2.4 -0.5 0 0 0 10 Typical +1.8 +3.3 +1.8 Maximum +1.95 +3.6 +1.95 VDD OVDD+0.5 +5.5 0.65VDD 0.35OVDD +0.8 OVDD OVDD 0.35OVDD +0.4 0 200 -325 VDD + 0.6 +5.5 Unit V V V V V V V V V V V V V Notes
A A A
V V V V V
C
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5V-Tolerant Input Current
50 0 -50 Input Current (A)
-100 -150
-200
-250
-300 -350 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V)
Input Capacitance
Parameter 3.3V LVTTL I/O 5V tolerant, 3.3V LVTTL I/O PCI I/O Rx only pins IIC pads Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Maximum 12 12 12 9 6.7 Unit pF pF pF pF pF Notes
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DC Electrical Characteristics
Parameter Active Operating Current (VDD) Active Operating Current (OVDD) Active Operating Current (AVDD) Total Power Note: 1. AVDD should be derived from VDD using the following circuit: Symbol IDD IODD IADD PT Minimum 440 59 14 1 Typical 520 70 17 1.2 Maximum 606 81 19 1.4 Unit mA mA mA W
VDD L1
AVDD
+ C1 C2 C3
AGND
L1 - 2.2H SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 - 3.3 F SMT tantalum C2 - 0.1F SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 F SMT monolithic ceramic capacitor with X7R dielectric or equivalent
GND
Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." For all signals other than PCI signals, AC specifications are characterized at OVDD = 3V and TC = 85C with the 50pF test load shown in the figure at right. For PCI signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right.
Output Pin
50pF
All signals other than PCI
Output Pin
PCI Rising edge
10pF
25
Output Pin
25 10pF
OVDD
PCI Falling edge
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Clocking Specifications
Symbol SysClk Input FC TC TCS TCH TCL Frequency Period Edge stability (phase jitter, cycle to cycle) Input high time Input low time 25 7.5 - 133 40 0.15 MHz ns ns ns ns Parameter Min Max Units
40% of nominal period 60% of nominal period 40% of nominal period 60% of nominal period
Note: Input slew rate > 2V/ns MemClkOut Output FC TC TCH TCL Frequency Period Output high time Output low time 7.50 35% of nominal period 65% of nominal period 35% of nominal period 65% of nominal period 133 MHz ns ns ns
Clocking Waveform
TCH TC
TCL
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Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405EP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405EP the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405EP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405EP peripherals impose more stringent requirements (see Note 1). * Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the SDRAM MemClkOut since it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation 2. Operation of the PPC405EP PCI Bridge is unaffected by the use of an SSCG. The PCI controller must be operated in asynchronous mode. When in asynchronous mode, the PCI bus clock must be driven into the PPC405EP PCIClk input. In this configuration the PCI controller supports the 66.66 MHz PCI clock specification which specifies a maximum frequency deviation of -1% at a modulation of between 30 kHz and 33 kHz. 3. Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405EP meets the above requirements and does not adversely affect other aspects of the system.
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Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input low time EMC0MDClk output frequency EMC0MDClk period EMC0MDClk output high time EMC0MDClk output low time PHY0Tx0:1Clk input frequency PHY0Tx0:1Clk period PHY0Tx0:1Clk input high time PHY0Tx0:1Clk input low time PHY0Rx0:1Clk input frequency PHY0Rx0:1Clk period PHY0Rx0:1Clk input high time PHY0Rx0:1Clk input low time PerClk output frequency PerClk period PerClk output high time PerClk output low time PerClk clock edge stability (phase jitter, cycle to cycle) Note: 1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405EP Embedded Processor User's Manual for more information. Min Note 1 15 40% of nominal period 40% of nominal period - 400 160 160 2.5 40 35% of nominal period 35% of nominal period 2.5 40 35% of nominal period 35% of nominal period - 20 50% of nominal period 33% of nominal period Max 66.66 Note 1 60% of nominal period 60% of nominal period 2.5 - - - 25 400 - - 25 400 - - 50 - 66% of nominal period 50% of nominal period 0.3 Units MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns ns
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Input Setup and Hold Timing Waveform
System Clock
TIS MIN Inputs Valid
TIH MIN
Output Delay and Float Timing Waveform
System Clock TOV MAX TOH MIN
Outputs Valid MAX MIN
TOF
Outputs
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Notes: 1. In the following I/O Specifications tables a timing value of na means "not applicable" and dc means "don't care." 2. See "Test Conditions" on page 42 for output capacitive loading.
I/O Specifications--Group 1 (Part 1 of 2) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User's Manual. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal PCI Interface PCIAD31:00 PCIC3:0/BE3:0 PCIClk PCIDevSel PCIFrame PCIGnt0/Req PCIGnt1:2 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0/Gnt PCIReq1:2 PCIReset PCISErr PCIStop PCITRDY Ethernet Interface EMC0MDClk EMC0MDIO EMC0Tx0:1D3:0 EMC0Tx0:1En EMC0Tx0:1Err PHY0Col0:1 PHY0CrS0:1 PHY0Rx0:1Clk PHY0Rx0:1D3:0 PHY0Rx0:1DV PHY0Rx0:1Err PHY0Tx0:1Clk na 100 na na na 2 2 na 2 2 2 na na 0 na na na 3 3 na 4 4 4 na settable 2 10.3 10.3 10.3 10.3 10.3 na na na na na na na 7.1 7.1 7.1 7.1 7.1 na na na na na na na async EMC0MDClk PHY0TxClk PHY0TxClk PHY0TxClk PHY0RxClk PHY0RxClk async PHY0RxClk PHY0RxClk PHY0RxClk async 2 2 2 2 2 2 2 2 2 2 2 2 1 OPB clock 1 OPB clock period + 10ns period 14 14 14 na na na na na na na 5 5 5 na na na na na na na 3 3 na 3 3 na 3 na 3 3 3 5 na na 3 3 0 0 na 0 0 na 0 na 0 0 0 0 na na 0 0 6 6 na 6 6 6 na na 6 6 6 na na na 6 6 1 1 na 1 1 1 na na 1 1 1 na na na 1 1 0.5 0.5 na 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 1.5 1.5 na 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 PCIClk PCIClk async PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (min) I/O L (min) Clock Notes
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I/O Specifications--Group 1 (Part 2 of 2) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User's Manual. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na na na Hold Time (TIH min) na na na na na na na na Output (ns) Valid Delay (TOV max) na na na na na na na na Hold Time (TOH min) na na na na na na na na Output Current (mA) I/O H (min) 15.3 15.3 na 10.3 na 10.3 na 10.3 10.3 na na na na na na na na na na 3 na na na na na na na na na na na 1 na na na na na na na na na na na na na na na na na na na na na na na na na na na 10.3 na na 10.3 na 10.3 10.3 na na na I/O L (min) 10.2 10.2 na 7.1 na 7.1 na 7.1 7.1 na na 7.1 na na 7.1 na 7.1 7.1 na na na async async async async async async async async async async Clock Notes
Internal Peripheral Interface IICSCL IICSDA UART0_CTS UART0_RTS UART0_Rx UART0_Tx UART1_Rx UART1_Tx Interrupts Interface [IRQ0:6] JTAG Interface TCK TDI TDO TMS TRST System Interface GPIO00:31 Halt SysErr SysReset TestEn [RejectPkt0:1] SysClk
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I/O Specifications--Group 2
Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal SDRAM Interface BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 MemAddr12:00 MemData00:31 RAS WE PerAddr06:31 [PerBLast] PerCS0 [PerCS1:4] PerData00:31 PerOE PerR/W PerReady PerWBE0:3 ExtReset PerClk na na na na na na 1.6 na na na 4 na 5 na na 6.5 na na na na na na na na na 1 na na na 1 na 1 na na 1 na na na 4.7 4.5 4.8 4.1 4.7 4.8 4 5 4.9 3.8 8 4.1 6.4 4.1 4.1 na 4.1 na 0.4 2 1.7 2 1.6 1.9 2.1 1.2 2.1 2 1.6 0 1.5 1.5 1.5 1.6 na 1.6 na -0.2 15.3 15.3 15.3 28.7 15.3 15.3 15.3 15.3 15.3 15.3 12 10.3 15.3 10.3 10.3 na 10.3 15.3 15.3 10.2 10.2 10.2 19.3 10.2 10.2 10.2 10.2 10.2 10.2 8 7.1 10.2 7.1 7.1 na 7.1 10.2 10.2 MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk 4 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (minimum) I/O L (minimum) Clock Notes
External Slave Peripheral Interface
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Initialization
The following describes the method by which initial chip settings are established when a system reset occurs. Strapping When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405EP start-up. The actual capture instant is the nearest system clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to +5V. The recommended pull-down is 1K to GND. These pins are use for strap functions only during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation follow the pin number.
Strapping Pin Assignments
Function SEPROMPresent - Serial EEPROM connection to the IIC interface Not connected Connected Option Ball Strapping P04 UART0_Tx 0 1 N02 UART0_RTS When SEPROMPresent = 1, these pins set the highorder two bits of the EEPROM base address. When SEPROMPresent = 0, these pins indicated the width of the boot ROM. High order EEPROM base address bits 8 bits 16 bits reserved reserved x 0 0 1 1 Y17 SysErr x 0 1 0 1
EEPROM During reset, configuration values other than those obtained from the strapping pins can be read from a serial EEPROM connected to the IIC port. The association of bits in the EEPROM with the configuration values and their default values are covered in detail in the PowerPC 405EP Embedded Processor User's Manual. Caution: If SEPROMPresent is strapped to 1, and the EEPROM is not connected or is defective, the PPC405EP remains in the reset state and will not boot up.
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Inside of back cover
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(c) Copyright International Business Machines Corporation 1999, 2002
All Rights Reserved Printed in the United States of America, 10/22/02 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both:
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Other company, product, and service names may be trademarks or service marks of others. Preliminary Edition (10/22/02) This document contains information on a new product under development by IBM. IBM reserves the right to change or discontinue this product without notice. This document is a preliminary edition of the PowerPC 405EP data sheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52 Hopewell Junction, NY 12533-6351 The IBM home page is www. ibm.com. The IBM Microelectronics Division home page is www.chips.ibm.com. SA14-2704-00

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